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Memory control register 0B
Register symbol: MEMCTR0B
Address:
x'32000020
Purpose:
Sets the bus mode, access timing, etc., for external memory space block 0.
Bit No.
15
14
Bit
B0
B0
name
WEN4WEN3WEN2WEN1WEN0 ASN2 ASN1 ASN0 ASA1 ASA0
Reset
1
1
Access
R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W
Bit No.
Bit name
2
BM
7 to 6
ASA1 to 0
10 to 8
ASN2 to 0
15 to 11
WEN4 to 0
After the reset is released, block 0 is set as follows:
Synchronous mode
Address output end timing
RE negate timing
WE negate timing
RE/WE assert timing
Bus cycle start timing
Bus cycle end timing
AS assert timing
AS negate timing
The bus width is the bus width (8 bits or 16 bits) that accords with the mode specified by the MMOD1 and 0 pins
and the EXMOD1 and 0 pins.
Note: For details on the setting of the MMOD1 and 0 pins and the EXMOD1 and 0 pins, refer to section 8.9,
"Mode Settings."
13
12
11
10
B0
B0
B0
B0
B0
1
0
1
0
Description
Block 0 bus mode
AS assert timing
AS negate timing
Set so that:
ASN
ASA
WE negate timing
Set so that:
WEN EA
3MCLK
29MCLK
29MCLK
3MCLK
0MCLK
31MCLK
1MCLK
3MCLK
9
8
7
6
5
B0
B0
B0
–
1
1
0
1
0
R
Setting conditions
0: Synchronous mode (SYSCLK synchronization)
1: Asynchronous mode (MCLK synchronization)
00: 0MCLK
11: 3MCLK
000: prohibited
001: 1MCLK
111: 7MCLK
Settings other than those shown below are prohibited.
00011: 3MCLK
11111: 31MCLK
Bus Controller (BC)
4
3
2
1
0
B0
–
–
–
–
BM
0
0
0
0
0
R
R
R/W
R
R
8-9
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