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9.4 Block Diagram
CPU core
Level: 0 to 6
The interrupt level can be set separately for
each group. (However, GROUP 0 and
GROUP 1 are non-maskable.)
Non-maskable
interrupts
GROUP
0
GROUP
1
GROUP
2
GROUP
3
GROUP
4
GROUP
5
GROUP
6
Fig. 9-4-1 Block Diagram 1
0
NMIRQ pin
1
Watchdog timer overflow
System error
2
—
3
0
1
Reserved for system
2
3
0
Timer 0 underflow
Timer 1 underflow
1
Timer 2 underflow
2
Timer 3 underflow
3
0
Timer 4 underflow
Timer 5 underflow
1
Timer 6 underflow
2
Timer 7 underflow
3
0
Timer 8 underflow
Timer 9 underflow
1
Timer A underflow
2
Timer B underflow
3
0
Timer 10 overflow
Timer 10 compare/capture A
1
Timer 10 compare/capture B
2
—
3
Timer 11 underflow
0
1
Timer 12 underflow
Timer 13 underflow
2
—
3
Interrupt Controller
Interrupt control
register address
x'34000100
x'34000108
x'3400010C
x'34000110
x'34000114
x'34000118
9-3
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