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When using DRAM (Memory control register 1B B1DRAM = 1)
Bit No.
Bit name
0
DRAM
2
BM
3
PE
4
BW
7 to 6
ASA1 to 0
10 to 8
ASN2 to 0
15 to 11
WEN4 to 0
After the reset is released, block 1 is set as follows:
Address output end timing
RE negate timing
WE negate timing
RE/WE assert timing
Bus cycle start timing
Bus cycle end timing
AS assert timing
AS negate timing
The bus width is 16 bits, and synchronous mode is set.
Description
Block 1 DRAM
space setting
Block 1 bus mode
Block 1 software page
mode enable
Block 1 bus width
Always set to "01".
RAS precharge cycle
(use as RP parameter)
WE negate timing
Set so that:
CAO (ADE)+CAS (REN)
WEN
3MCLK
29MCLK
29MCLK
3MCLK
0MCLK
31MCLK
1MCLK
3MCLK
Setting conditions
1: Use as DRAM space.
1: Asynchronous mode (MCLK synchronization)
0: Disabled
1: Enabled
0: 8 bits
1: 16 bits
Any setting other than "01" is prohibited.
000: prohibited
001: 1MCLK
111: 7MCLK
Settings other than those shown below are prohibited.
00100: 4MCLK
11111: 31MCLK
Bus Controller (BC)
8-13
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