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Bus Controller (BC)
Memory control register 2B
Register symbol: MEMCTR2B
Address:
x'32000024
Purpose:
Sets the bus mode, access timing, etc., for external memory space block 2.
Bit No.
15
14
Bit
B2
B2
name
WEN4WEN3WEN2WEN1WEN0 ASN2 ASN1 ASN0 ASA1 ASA0
Reset
1
1
Access
R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W
Bit No.
Bit name
0
DRAM
1
WM
2
BM
3
PE
4
BW
7 to 6
ASA1 to 0
10 to 8
ASN2 to 0
15 to 11
WEN4 to 0
8-16
13
12
11
10
B2
B2
B2
B2
1
0
1
0
When using fixed wait mode and not using DRAM
(Memory control register 2B B2DRAM = 0, B2WM = 0)
Description
Block 2 DRAM
space setting
Block 2 wait mode
Block 2 bus mode
Block 2 software page
mode enable
Block 2 bus width
AS assert timing
AS negate timing
Set so that:
ASN ASA
WE negate timing
Set so that:
WEN
EA
9
8
7
6
B2
B2
B2
B2
1
1
0
1
Setting conditions
0: Do not use as DRAM space.
0: fixed wait mode
0: Synchronous mode (SYSCLK synchronization)
1: Asynchronous mode (MCLK synchronization)
Not using
0: 8 bits
1: 16 bits
Settings other than those shown below are prohibited.
00011: 3MCLK
11111: 31MCLK
5
4
3
2
B2
B2
B2
B2
–
BW
PE
BM
WM DRAM
0
1
0
0
R
R/W R/W R/W R/W R/W
00: 0MCLK
11: 3MCLK
000: prohibited
001: 1MCLK
111: 7MCLK
1
0
B2
0
0
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