Fig. 8-13-27 Access Timing On A 8-Bit Bus With Handshaking, In Synchronous Mode And In Address/Data Multiplex Mode (Mclk = Sysclk Multiplied By 4) - Panasonic MN103001G/F01K User Manual

MCLK
SYSCLK
A23* to 16
A[0]=0
ADM15 to 0
A[0]=0
CSn
ASA
AS
ASN
RWSEL
RE
"H"
WE0
DK
: Undefined
: Undefined or Hi-Z
*
: A23 also serves as CS3
MCLK
SYSCLK
A23* to 16
A[0]=0
ADM15 to 0
A[0]=0
CSn
ASA
AS
ASN
RWSEL
RE
"H"
WE0
DK
: Undefined
: Undefined or Hi-Z
*
: A23 also serves as CS3
Fig. 8-13-27 Access Timing on a 8-bit Bus with Handshaking, in Synchronous Mode and in Address/
For details on the various timing settings, refer to the description of the memory control register in section 8.6,
"Description of Registers."
"0" ("L")
ADE
Consumed internally
DW
by the BC
DK detection start
EA
Read low-order side
(a) Read Timing
"0" ("L")
data out
ADE
Consumed internally Consumed internally
DW
by the BC by the BC
DK detection start
EA
Write low-order side
(b) Write Timing
Data Multiplex Mode (MCLK = SYSCLK multiplied by 4)
A[0]=1
data in A[0]=1
ADE
BCE ASA
ASN
REN
Read high-order side
A[0]=1
A[0]=1
ADE
BCE ASA
ASN
WEN
Write high-order side
Bus Controller (BC)
"0" ("L")
data in
BCE
Consumed internally
DW
by the BC
DK detection start
REN
EA
"0" ("L")
data out
BCE
Consumed internally
DW
by the BC
DK detection start
WEN
EA
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