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Bus Controller (BC)
When using handshaking mode (Memory control register 3B B3WM = 1)
Bit No.
Bit name
1 to 0
BCS1 to 0
3 to 2
EA1 to 0
5 to 4
ADE1 to 0
10 to 6
BCE4 to 0
15 to 11
REN4 to 0
Note: Handshaking mode can only be set when (MCLK frequency/SYSCLK frequency) = 4.
If (MCLK frequency/SYSCLK frequency) = 1 or 2, set B3WM = 0 in MEMCTR3B.
Memory control register 3B
Register symbol: MEMCTR3B
Address:
x'32000026
Purpose:
Sets the bus mode, access timing, etc., for external memory space block 3.
Bit No.
15
14
Bit
B3
B3
name
WEN4WEN3WEN2WEN1WEN0 ASN2 ASN1 ASN0 ASA1 ASA0
Reset
1
1
Access
R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W
When using fixed wait mode (Memory control register 3B B3WM = 0)
Bit No.
Bit name
1
WM
2
BM
4
BW
7 to 6
ASA1 to 0
10 to 8
ASN2 to 0
15 to 11
WEN4 to 0
8-20
DK detection wait cycle (used as parameter DW)
RE/WE assert timing
Address output end timing
Bus cycle end timing
Set so that:
BCE
REN, BCE WEN
RE negate timing
13
12
11
10
B3
B3
B3
B3
1
0
1
0
Description
Block 3 wait mode
Block 3 bus mode
Block 3 bus width
AS assert timing
AS negate timing
Set so that:
ASN ASA
WE negate timing
Set so that:
WEN
EA
Description
9
8
7
6
B3
B3
B3
B3
1
1
0
1
Setting conditions
0: fixed wait mode
0: Synchronous mode (SYSCLK synchronization)
1: Asynchronous mode (MCLK synchronization)
0: 8 bits
1: 16 bits
Settings other than those shown below are prohibited.
00011: 3MCLK
11111: 31MCLK
Setting conditions
00: prohibited
01: 1MCLK
10: 2MCLK
11: 3MCLK
00: prohibited
01: 1MCLK
10: 2MCLK
11: 3MCLK
00: 0MCLK
11: 3MCLK
00000: 0MCLK
11111: 31MCLK
00000: 0MCLK
11111: 31MCLK
5
4
3
2
B3
B3
B3
–
–
BW
BM
WM
0
1
0
0
R
R/W
R
R/W R/W
00: 0MCLK
11: 3MCLK
000: prohibited
001: 1MCLK
111: 7MCLK
1
0
–
0
0
R
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