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Chapter 4 Timer Functions
The upper 2 bits of the watchdog
timer are cleared when the WDEN
flag is set to "0." Therefore, if
WDEN flag is set to 0 when an
uppermost bit of a watchdog timer
is 1, WDT interrupt occurs
depending on the timing of this
clear the watchdog timer may be
reset at 1/4T
. If the WDEN bit is
WD
to be repeatedly cleared and set at
regular intervals, those operations
should be performed within 1/4 of
the T
period.
WD
78
Watchdog Timer Operation
4-6 Watchdog Timer Operation
4-6-1 Overview
The watchdog timer is controlled by the watchdog control register (WDCTR) and can
be used for runaway program detection.
4-6-2 Setup and Operation
(1)
Set the WDEN flag of the watchdog timer control register (WDCTR) to "1" to start
the watchdog timer.
(2)
Operate the watchdog timer by clearing the WDEN flag to "0" within the fixed
amount of time (T
WD
If the WDEN flag is not cleared, a WDT interrupt will be generated after the fixed
amount of time passes.
(3)
When an illegal operation is detected, the program encoded at the location of the
WDT interrupt routine is executed.
T
is set by the ROM option as fs/2
WD
Illegal operation detection period vs. WDEN clear period is shown by the following formula:
Illegal operation detection period > [WDEN clear period] x 4
When software resetting is not triggered by WDT interrupt,
hardware resetting (low level output at the reset terminal) takes
place at the next WDT interrupt.
), and then resetting the WDEN flag to "1."
16
, fs/2
18
, or fs/2
20
.
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