64-Bit Addressing In Scripts; Hardware Control Of Scsi Activity Led - LSI LSI53C875A Technical Manual

2.2.3 64-Bit Addressing in SCRIPTS

2.2.4 Hardware Control of SCSI Activity LED

The LSI53C875A has a 32-bit PCI interface which provides 64-bit
address capability in the initiator mode.
DACs can be generated for all SCRIPTS operations. There are six
selector registers which hold the upper Dword of a 64-bit address. All but
one of these is static and requires manual loading using a CPU access,
a Load/Store instruction, or a Memory Move instruction. One of the
selector registers is dynamic and is used during 64-bit direct block moves
only. All selectors default to zero, meaning the LSI53C875A powers-up
in a state where only Single Address Cycles (SACs) are generated.
When any of the selector registers are written to a nonzero value, DACs
are generated.
Direct, Table Indirect and Indirect Block moves, Memory-to-Memory
Moves, Load and Store instructions, and jumps are all instructions with
64-bit address capability.
Crossing the 4 Gbyte boundary on any one SCRIPTS operation is not
permitted and software needs to take care that any given SCRIPTS
operation will not cross the 4 Gbyte boundary.
The LSI53C875A has the ability to control a LED through the GPIO_0
pin to indicate that it is connected to the SCSI bus. Formerly this function
was done by a software driver.
When bit 5 (LED_CNTL) in the
(GPCNTL0) register is set and bit 6 (Fetch Enable) in the
Purpose Pin Control Zero (GPCNTL0)
LSI53C875A is not performing an EEPROM autodownload, then bit 3
(CON) in the Interrupt Status Zero (ISTAT0)
GPIO_0 pin.
The CON (Connected) bit in
the LSI53C875A is connected to the SCSI bus either as an initiator or a
target. This will happen after the LSI53C875A has successfully
completed a selection or when it has successfully responded to a
selection or reselection. It will also be set when the LSI53C875A wins
arbitration in low level mode.
SCSI Functional Description
General Purpose Pin Control Zero
register is cleared and the
register is presented at the
Interrupt Status Zero (ISTAT0)
General
is set anytime
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