Scsi Registers - LSI LSI53C875A Technical Manual

4.2 SCSI Registers

4-18
Register: 0x47
Data
Read Only
7
0 0
DATA Data
This register provides an optional mechanism for the
function to report state-dependent operating data. The
LSI53C875A does not use this register and always
returns 0x00.
The control registers for the SCSI core are directly accessible from the
PCI bus using Memory or I/O mapping. The address map of the SCSI
registers is shown in
Note: The only registers that the host CPU can access while the
LSI53C875A is executing SCRIPTS are the
Zero (ISTAT0),
Mailbox Zero
attempts to access other registers interfere with the
operation of the chip. However, all operating registers are
accessible with SCRIPTS. All read data is synchronized
and stable when presented to the PCI bus.
Registers
DATA
0 0 0
Table 4.2.
Interrupt Status One (ISTAT1)
(MBOX0), Mailbox One (MBOX1)
0
0 0 0
[7:0]
Interrupt Status
and
registers;