Appendix A Register Summary; A.1 Lsi53C875A Pci Register Map - LSI LSI53C875A Technical Manual

Table A.1 LSI53C875A PCI Register Map
Register Name
Base Address Register One (MEMORY)
Base Address Register Two (SCRIPTS RAM)
Base Address Register Zero (I/O)
Bridge Support Extensions (PMCSR_BSE)
Cache Line Size
Capabilities Pointer
Capability ID
Class Code
Command
Data
Device ID
Expansion ROM Base Address
Header Type
Interrupt Line
Interrupt Pin
Latency Timer
Max_Lat
Min_Gnt
Next Item Pointer
Appendix A
Register Summary
LSI53C875A PCI to Ultra SCSI Controller
Address Read/Write Page
0x14–0x17 Read/Write
0x18–0x1B Read/Write
0x10–0x13 Read/Write
0x46 Read Only
0x0C Read/Write
0x34 Read Only
0x40 Read Only
0x09–0x0B Read Only
0x04–0x05 Read/Write
0x47 Read Only
0x02–0x03 Read Only
0x30–0x33 Read/Write
0x0E Read Only
0x3C Read/Write
0x3D Read Only
0x0D Read/Write
0x3F Read Only
0x3E Read Only
0x41 Read Only
4-9
4-10
4-9
4-17
4-7
4-13
4-15
4-7
4-3
4-18
4-3
4-12
4-8
4-13
4-14
4-8
4-14
4-14
4-15
A-1