Determining The Synchronous Transfer Rate - LSI LSI53C875A Technical Manual

Figure 2.6

Determining the Synchronous Transfer Rate

SCF2
0
0
0
1
0
1
1
1
Clock
SCLK
Quadrupler
Example 1 (using 40 MHz clock)
SCLK = 40 MHz
QCLK (Quadrupled SCSI Clock) = 160 MHz
SCF = 1 (/1), XFERP = 4 (/8), CCF = 7 (/8)
Synchronous send rate = (QCLK/SCF)/XFERP =
1
(160/1) /8 = 20 Mbytes/s
Synchronous receive rate = (QCLK/SCF) /4 =
2
(160/1) /4 = 40 Mbytes/s
Note:
Synchronous send rate must not exceed 20 Mbytes/s because the
LSI53C875A is an Ultra SCSI device.
Although maximum synchronous receive rate is 40 Mbytes/s the
maximum transfer rate is 20 Mbytes/s because the LSI53C875A is an
Ultra SCSI device.
SCF1 SCF0 SCF
Divisor
0 1 1
1 0 1.5
1 1 2
0 0 3
0 0 3
0 1 4
1 0 6
1 1 8
QCLK
CCF2 CCF1 CCF0
0 0 1
0 1 0
0 1 1
1 0 0
0 0 0
1 0 1
1 1 0
1 1 1
SCSI Functional Description
TP2
0
0
0
0
1
1
1
1
This point
must not
Divide by 4
exceed
160 MHz
Synchronous
SCF
Divider
CCF Asynchronous
Divider SCSI Logic
Divisor QCLK (MHz)
1 50.1–66.00
1.5 16.67–25.00
2 25.1–37.50
3 37.51–50.00
3 50.01–66.00
4 75.01–80.00
6 120
8 160
Example 2 (using 20 MHz clock)
SCLK = 20 MHz
QCLK (Quadrupled SCSI Clock) = 80 MHz
SCF = 1 (/1), XFERP = 0 (/4), CCF = 5 (/4)
Synchronous send rate = (QCLK/SCF)/XFERP =
(80/1) /4 = 20 Mbytes/s
Synchronous receive rate = (QCLK/SCF) /4 =
(80/1) /4 = 20 Mbytes/s
TP1 TP0 XFERP
Divisor
0 0 4
0 1 5
1 0 6
1 1 7
0 0 8
0 1 9
1 0 10
1 1 11
Receive
Clock
Send Clock
Divider
(to SCSI Bus)
This point must
not exceed 20 MHz.
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