Initiator Timing; Nonburst Opcode Fetch, 32-Bit Address And Data - LSI LSI53C875A Technical Manual

6.4.2 Initiator Timing

Table 6.21

Nonburst Opcode Fetch, 32-Bit Address and Data

Symbol Parameter
t Shared signal input setup time
1
t Shared signal input hold time
2
t CLK to shared signal output valid
3
t Side signal input setup time
4
t Side signal input hold time
5
t CLK to side signal output valid
6
t CLK HIGH to GPIO0_FETCH/ LOW
7
t CLK HIGH to GPIO0_FETCH/ HIGH
8
t CLK HIGh to GPIO1_MASTER/ LOW
9
t CLK HIGH to GPIO1_MASTER/ HIGH
10
The tables and figures in this section describe LSI53C875A initiator
timings.
PCI and External Memory Interface Timing Diagrams
Min Max
7 –
0 –
2 11
10 –
0 –
2 12
– 20
– 20
– 20
– 20
Unit
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
6-19