Table 6.26
Burst Read, 64-Bit Address and Data
Symbol
Parameter
t
Shared signal input setup time
1
t
Shared signal input hold time
2
t
CLK to shared signal output valid
3
t
CLK HIGH to GPIO1_MASTER/HIGH
10
PCI and External Memory Interface Timing Diagrams
Min
Max
7
–
0
–
2
11
–
20
Unit
ns
ns
ns
ns
6-29