Pci Performance; Integration; Ease Of Use; Memory Move Instructions 5 - LSI LSI53C875A Technical Manual

1.4.2 PCI Performance

1.4.3 Integration

1.4.4 Ease of Use

1-6
Supports additional arithmetic capability with the Expanded Register
Move instruction.
To improve PCI performance, the LSI53C875A:
Complies with PCI 2.2 specification.
Supports 32-bit 33 MHz PCI interface with 64-bit addressing.
Supports dual address cycles which can be generated for all
SCRIPTS for > 4 Gbyte addressability.
Bursts 2, 4, 8, 16, 32, 64, or 128 Dword transfers across the PCI bus.
Supports 32-bit word data bursts with variable burst lengths.
Prefetches up to 8 Dwords of SCRIPTS instructions.
Bursts SCRIPTS opcode fetches across the PCI bus.
Performs zero wait-state bus master data bursts faster than
110 Mbytes/s (@ 33 MHz).
Supports PCI Cache Line Size register.
Supports PCI Write and Invalidate, Read Line, and Read Multiple
commands.
Complies with PCI Bus Power Management Specification Rev 1.1.
Features of the LSI53C875A which ease integration include:
High-performance SCSI core.
Integrated SE transceivers.
Full 32-bit PCI DMA bus master.
Integrated SCRIPTS processor.
Memory-to-Memory Move instructions allow use as a third party PCI
bus DMA controller.
The LSI53C875A provides:
General Description