Power And Ground Signals - LSI LSI53C875A Technical Manual

3.8 Power and Ground Signals

Table 3.14

Power and Ground Signals

Name PQFP
VSS_I/O 4, 10, 14, 18,
23, 27, 31, 37,
42, 48, 69, 79,
88, 93, 99,
104, 109, 114,
123, 133, 152,
158
VDD_I/O 8, 21, 33, 45,
63, 74, 84,
118, 128, 138,
155
VDD_CORE 51, 83, 149
VSS_CORE 55, 80, 146
VDDA 129
VSSA 132
NC 72, 73, 75, 76,
78, 81, 82,
119–122, 124,
125, 134, 135
Note:
The I/O driver pad rows and digital core have isolated power supplies as indicated by the "I/O"
and "CORE" extensions on their respective V
should be connected directly to the primary power and ground planes of the circuit board. Bypass
capacitors of 0.01 F should be applied between adjacent V
Do not connect bypass capacitors between V
boundaries.
Table 3.14 describes the Power and Ground signals.
BGA
A9, B11, D12,
E13, F12,
G11, J13,
K10, K12, N9
B10, C12, D2,
D5, E8, G1,
J5, J7, K1,
L11, M10
A5, L5, L12
C6, L6, N12
D9
B9
A12, A13, B2,
B3, B12, B13,
C3, C8, C11,
D1, D8, D10,
E9, F4-6, G5,
H4, H8, J3,
K3, K9, M2,
M4, M11-13,
N2, N10, N11,
N13
Power and Ground Signals
Type Strength Description
G N/A Ground for PCI bus
drivers/receivers, SCSI bus
drivers/receivers, local memory
interface drivers, and other I/O
pins.
P N/A Power for PCI bus
drivers/receivers, SCSI bus
drivers/receivers, local memory
interface drivers/receivers, and
other I/O pins.
P N/A Power for core logic.
G N/A Ground for core logic.
P N/A Power for analog cells (clock
quadrupler and diffsense logic).
G N/A Ground for analog cells (clock
quadrupler and diffsense logic).
N/A N/A These pins have NO internal
connection.
and V names. These power and ground pins
SS DD
and V
SS
and V pairs that cross power and ground bus
SS DD
pairs wherever possible.
DD
3-13