Dma Fifo; Parity Checking/Generation - LSI LSI53C875A Technical Manual

Figure 2.2

Parity Checking/Generation

Asynchronous
SCSI Send
PCI Interface**
X

DMA FIFO*

(64 bits X 118)
SODL Register*
S
SCSI Interface**
X = Check parity
G = Generate 32-bit even PCI parity
S = Generate 8-bit odd SCSI parity
2.2.12 DMA FIFO
Asynchronous
SCSI Receive
PCI Interface**
G
DMA FIFO*
(64 bits X 118)
SIDL Register*
X
SCSI Interface**
The DMA FIFO is 8 bytes wide by 118 transfers deep. The DMA FIFO is
illustrated in Figure
assure compatibility with older products in the LSI53C8XX family.
The DMA FIFO size may be set to 944 bytes by setting the DMA FIFO
Size bit, bit 5, in the
SCSI Functional Description
Synchronous
SCSI Send
PCI Interface**
X
DMA FIFO*
(64 bits X 118)
SODL Register*
SODR Register*
S
SCSI Interface**
2.3. The default DMA FIFO size is 112 bytes to
Chip Test Five (CTEST5)
Synchronous
SCSI Receive
PCI Interface**
G
DMA FIFO*
(64 bits X 118)
X
SCSI FIFO**
(8 or 16 bits x 31)
X
SCSI Interface**
* = No parity protection
** = Parity protected
register.
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