Bit Address Operating Register/Scripts Ram Read - LSI LSI53C875A Technical Manual

Table 6.18

64-Bit Address Operating Register/SCRIPTS RAM Read

Symbol Parameter
t Shared signal input setup time
1
t Shared signal input hold time
2
t CLK to shared signal output valid
3
Figure 6.12 64-Bit Address Operating Register/SCRIPTS RAM Read
CLK
(Driven by System)
FRAME/
(Driven by Master)
AD[31:0]
(Driven by Master-Addr;
LSI53C875A-Data)
C_BE[3:0]
(Driven by Master)
PAR
(Driven by Master-Addr;
LSI53C875A-Data)
IRDY/
(Driven by Master)
TRDY/
(Driven by LSI53C875A)
STOP/
(Driven by LSI53C875A)
DEVSEL/
(Driven by LSI53C875A)
6-16
t
1
t
1
Addr Addr
Lo Hi
t
2
t t
1 1
Dual Bus
Addr CMD
t
1
In In
t
2
t
1
Electrical Specifications
Byte Enable
t
3
Min Max
7 –
0 –
– 11
t
3
Data
Out
t
2
Out
t
2
t
3
t
3
Unit
ns
ns
ns
t
2
t
3