Pci Cache Mode Alignment - LSI LSI53C875A Technical Manual

2-12
Multiple Memory Write and Invalidates.
A single data residual Memory Write to complete the transfer.
Table 2.2 describes PCI cache mode alignment.
Table 2.2

PCI Cache Mode Alignment

Host Memory
A
B
C
D
E
G
H
Functional Description
00h
04h
08h
0Ch
10h
14h
18h
1Ch
20h
24h
28h
2Ch
F 30h
34h
38h
3Ch
40h
44h
48h
4Ch
50h
54h
58h
5Ch
60h