B.4 512 Kbyte Interface With 150 Ns Memory - LSI LSI53C875A Technical Manual

Pci to ultra scsi controller
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Figure B.4
512 Kbyte Interface with 150 ns Memory
GPIO4
MWE/
MOE/
MAD[7:0]
Bus
LSI53C875A
MAS0/
MAS1/
MCE/
Note: MAD2 pulled LOW internally. MAD bus sense logic enabled for 512 Kbytes of slow memory (150 ns
devices, additional time required for HCT139 @ 33 MHz). The HCT374s may be replaced with HCT377s.
B-4
Optional - for Flash Memory only, not
required for EEPROMS.
+ 12 V
VPP
Control
MAD3
4.7 K
MAD1
4.7 K
MAD3
4.7 K
D0
8
HCT374
D7
CK
D0
8
HCT374
D7
CK
MAD[2:0]
Bus
D0
3
D2
HCT377
CK
E
External Memory Interface Diagram Examples
VPP
WE
OE
D[7:0]
D[7:0]
A[7:0]
V
DD
A0
A[15:8]
Q0
Q7
QE
A16
Q0
Q7
QE
Q0
Y0
A
Y1
Q2
B
Y2
Y3
GB
HCT139
27C010-15/28F010-15 Sockets
WE
WE
OE
OE
D[7:0]
D[7:0]
A0
A0
.
.
.
.
.
.
.
.
.
A16
A16
CE
CE
CE
WE
OE
D[7:0]
A0
.
.
.
A16
CE

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