Bits Used For Parity Control And Generation - LSI LSI53C875A Technical Manual

Table 2.3

Bits Used for Parity Control and Generation

Bit Name
Assert SATN/ on
Parity Errors
Enable Parity
Checking
Assert Even SCSI
Parity
Disable Halt on
SATN/ or a Parity
Error (Target Mode
Only)
Enable Parity Error
Interrupt
Parity Error
Status of SCSI
Parity Signal
SCSI SDP1 Signal
Latched SCSI Parity
Master Parity Error
Enable
Master Data Parity
Error
Master Data Parity
Error Interrupt
Enable
Location
SCSI Control Zero
(SCNTL0), Bit 1
SCSI Control Zero
(SCNTL0), Bit 3
SCSI Control One
(SCNTL1), Bit 2
SCSI Control One
(SCNTL1), Bit 5
SCSI Interrupt
Enable Zero
(SIEN0), Bit 0
SCSI Interrupt
Status Zero
(SIST0), Bit 0
SCSI Status Zero
(SSTAT0), Bit 0
SCSI Status Two
(SSTAT2), Bit 0
SSTAT 2, Bit 3 and
SCSI Status One
(SSTAT1), Bit 3
Chip Test Four
(CTEST4), Bit 3
DMA Status
(DSTAT), Bit 6
DMA Interrupt
Enable (DIEN),
Bit 6
SCSI Functional Description
Description
Causes the LSI53C875A to automatically assert SATN/
when it detects a SCSI parity error while operating as an
initiator.
Enables the LSI53C875A to check for parity errors. The
LSI53C875A checks for odd parity.
Determines the SCSI parity sense generated by the
LSI53C875A to the SCSI bus.
Causes the LSI53C875A not to halt operations when a
parity error is detected in target mode.
Determines whether the LSI53C875A generates an
interrupt when it detects a SCSI parity error.
This status bit is set whenever the LSI53C875A detects a
parity error on the SCSI bus.
This status bit represents the active HIGH current state of
the SCSI SDP0 parity signal.
This bit represents the active HIGH current state of the
SCSI SDP1 parity signal.
These bits reflect the SCSI odd parity signal
corresponding to the data latched into the
Data Latch (SIDL) register.
Enables parity checking during PCI master data phases.
Set when the LSI53C875A
target device signaling a parity error during a data phase.
By clearing this bit, a Master Data Parity Error does not
cause assertion of INTA/ (or INTB/), but the status bit is
set in the DMA Status (DSTAT)
SCSI Input
,
as a PCI master, detects a
register.
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