Test Interface Signals - LSI LSI53C875A Technical Manual

Table 3.12 ROM Flash and Memory Interface Signals (Cont.)
Name PQFP
MAD[7:0] 59–62,
64–67

3.7 Test Interface Signals

Table 3.13

Test Interface Signals

Name PQFP BGA Type Strength Description
TEST_HSC/ 126
TCK 130
TMS 57
TDI 142
TEST_RST/ 127
TDO 58
TRST/ 131
3-12
BGA Type Strength Description
L7, M7, I/O 4 mA
N7, K7,
M8, N8,
L8, K8
Table 3.13 describes Test Interface signals.
A11 I N/A
A10 I N/A
N6 I N/A
D7 I N/A
C10 I N/A
J6 O 4 mA
C9 I N/A
Signal Descriptions
Memory Address/Data Bus. This bus is used in
conjunction with the memory address strobe pins
and external address latches to assemble up to a
20-bit address for an external EEPROM or flash
memory. This bus will put out the least significant
byte first and finishes with the most significant bits.
It is also used to write data to a flash memory or
read data into the chip from external EEPROM/
flash memory. These pins have static pull-downs.
Test Halt SCSI Clock. For LSI Logic test purposes
only. Pulled HIGH internally. This signal can also
cause a full chip reset.
Test Clock. This pin provides the clock for the JTAG
test logic.
Test Mode Select. The signal received at TMS is
decoded by the TAP controller to control JTAG test
operations. This pin has a static pull-down.
Test Data In. Serial test instructions are received by
the JTAG test logic at this pin. This pin has a static
pull-down.
Test Reset. For test purposes only. Pulled HIGH
internally.
Test Data Out. This pin is the serial output for test
instructions and data from the JTAG test logic.
Test Reset. This pin provides a reset for JTAG Test
Logic. Pulled HIGH internally.