External Memory Timing; External Memory Read - LSI LSI53C875A Technical Manual

6.4.3 External Memory Timing

Table 6.29

External Memory Read

Symbol Parameter
t Shared signal input setup time
1
t Shared signal input hold time
2
t CLK to shared signal output valid
3
t Address setup to MAS/ HIGH
11
t Address hold from MAS/ HIGH
12
t MAS/ pulse width
13
t MCE/ LOW to data clocked in
14
t Address valid to data clocked in
15
t MOE/ LOW to data clocked in
16
t Data hold from address, MOE/, MCE/ change
17
t Data setup to CLK HIGH
19
The tables and figures in this section describe LSI53C875A external
timings. The External Memory Write timings start on
PCI and External Memory Interface Timing Diagrams
page 6-40.
Min Max
7 –
0 –
– 11
25 –
15 –
25 –
150 –
205 –
100 –
0 –
5 –
Unit
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
6-35