First Dword - LSI LSI53C875A Technical Manual

5.7.1 First Dword

31 29 28
DMA Command (DCMD)
IT[2:0] R
1 1 0 0 0 0
Indirect addresses are not allowed. A burst of data is fetched from
the source address, put into the DMA FIFO and then written out to
the destination address. The move continues until the byte count
decrements to zero, then another SCRIPTS is fetched from system
memory.
The DMA SCRIPTS Pointer Save (DSPS)
(DSA) registers are additional holding registers used during the Memory
Move. However, the contents of the
register are preserved.
25 24 23
Register
NF
0 x x x x x x x x x x x x x x x x x x x x x x x x x
IT[2:0] Instruction Type - Memory Move
The IT bit configuration (110) defines a Memory Move
Instruction Type.
R Reserved
These bits are reserved and must be zero. If any of these
bits are set, an illegal instruction interrupt occurs.
NF No Flush
When this bit is set, the LSI53C875A performs a Memory
Move without flushing the prefetch unit. When this bit is
cleared, the Memory Move instruction automatically
flushes the prefetch unit. Use the No Flush option if the
source and destination are not within four instructions of
the current Memory Move instruction.
Note: This bit has no effect unless the Prefetch Enable bit in the
DMA Control (DCNTL)
SCRIPTS instruction prefetching, see
TC[23:0] Transfer Counter
The number of bytes to transfer is stored in the lower
24 bits of the first instruction word.
Memory Move Instructions
and
Data Structure Address (DSA)
DMA Byte Counter (DBC)
Transfer Counter (TC) [23:0]
register is set. For information on
Data Structure Address
Register
[31:29]
[28:25]
Chapter 2.
[23:0]
0
24
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