Pci Configuration Register Map - LSI LSI53C875A Technical Manual

Table 4.1

PCI Configuration Register Map

31
Device ID
Status
Not Supported
Subsystem ID
Max_Lat
Power Management Capabilities (PMC)
Data
4-2
bits that are currently supported by the LSI53C875A are described in this
chapter. Reserved bits should not be accessed
16 15
Class Code
Header Type
Base Address Register Zero (I/O)
Base Address Register One (MEMORY)
Base Address Register Two (SCRIPTS RAM)
Not Supported
Not Supported
Not Supported
Reserved
Expansion ROM Base Address
Reserved
Reserved
Min_Gnt
Bridge Support Exten-
sions (PMCSR_BSE)
Not Supported
Registers: 0x00–0x01
Vendor ID
Read Only
15
0 0 0 1
VID Vendor ID
This 16-bit register identifies the manufacturer of the
device. The Vendor ID is 0x1000.
Registers
Vendor ID
Command
Latency Timer
bits [31:0]
Subsystem Vendor ID
Interrupt Pin
Next Item Pointer
Power Management Control/Status (PMCSR)
VID
0 0 0 0 0
.
Revision ID (Rev ID)
Cache Line Size
Capabilities Pointer
Interrupt Line
Capability ID
0 0 0 0 0
0
0x00
0x04
0x08
0x0C
0x10
0x14
0x18
0x1C
0x20
0x24
0x28
0x2C
0x30
0x34
0x38
0x3C
0x40
0x44
0x48
0
0 0
[15:0]