First Dword - LSI LSI53C875A Technical Manual

5.8.1 First Dword

31 29 28 27 26 25 24 23 22
DMA Command (DCMD)
Register
IT[2:0] DSA R NF LS R
1 1 1 x 0 0
5-36
The SIOM and DIOM bits in the
whether the destination or source address of the instruction is in Memory
space or I/O space, as illustrated in the following table. The Load and
Store utilizes the PCI commands for I/O read and I/O write to access the
I/O space.
Bit
SIOM (Load)
DIOM (Store)
RA[6:0]
x x 0 x x x x
IT[2:0] Instruction Type
These bits should be 0b111, indicating the Load and
Store instruction.
DSA DSA Relative
When this bit is cleared, the value in the
Pointer Save (DSPS)
used to perform the Load and Store to/from. When this
bit is set, the chip determines the memory address to
perform the Load and Store to/from by adding the 24-bit
signed offset value in the
(DSPS)
R Reserved
NF No Flush (Store instruction only)
When this bit is set, the LSI53C875A performs a Store
without flushing the prefetch unit. When this bit is cleared,
the Store instruction automatically flushes the prefetch
unit. Use No Flush if the source and destination are not
within four instructions of the current Store instruction.
This bit has no effect on the Load instruction.
SCSI SCRIPTS Instruction Set
DMA Mode (DMODE)
Source
Memory
Register
16 15
DMA Byte Counter (DBC)
x x x 0 0 0 0 0 0
is the actual 32-bit memory address
to the Data Structure Address
register determine
Destination
Register
Memory
Register
R
0 0 0 0 0 0
DMA SCRIPTS
DMA SCRIPTS Pointer Save
(DSA).
3 2 0
BC
0 x x x
[31:29]
28
[27:26]
25