Dma Fifo Sections - LSI LSI53C875A Technical Manual

Figure 2.3

DMA FIFO Sections

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118
Transfers
Deep
8 Bits
Byte Lane 7
2.2.12.1 Data Paths
2-28
8 Bits 8 Bits
Byte Lane 6 Byte Lane 5
The LSI53C875A automatically supports misaligned DMA transfers. A
944-byte FIFO allows the LSI53C875A to support 2, 4, 8, 16, 32, 64, or
128 Dword bursts across the PCI bus interface.
The data path through the LSI53C875A is dependent on whether data is
being moved into or out of the chip, and whether SCSI data is being
transferred asynchronously or synchronously.
Figure 2.4 shows how data is moved to/from the SCSI bus in each of the
different modes.
Functional Description
8 Bytes Wide
8 Bits 8 Bits
Byte Lane 4 Byte Lane 3
8 Bits 8 Bits
Byte Lane 2 Byte Lane 1
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8 Bits
Byte Lane 0