Third Dword; Load And Store Instructions - LSI LSI53C875A Technical Manual

5.7.4 Third Dword

31
x x x x x x x

5.8 Load and Store Instructions

Temporary (TEMP)
x x x x x x x
TEMP Register
These bits contain the destination address for the
Memory Move.
The Load and Store instructions provide a more efficient way to move
data from/to memory to/from an internal register in the chip without using
the normal memory move instruction.
The Load and Store instructions are represented by two Dword opcodes.
The first Dword contains the
Counter (DBC) register values. The second Dword contains the
SCRIPTS Pointer Save (DSPS)
location of where to Load and Store, or the offset from the
Address (DSA), depending on the value of bit 28 (DSA Relative).
A maximum of 4 bytes may be moved with these instructions. The
register address and memory address must have the same byte
alignment, and the count set such that it does not cross Dword
boundaries. The memory address may not map back to the chip,
excluding RAM and ROM. If it does, a PCI read/write cycle occurs (the
data does not actually transfer to/from the chip), and the chip issues an
interrupt (Illegal Instruction Detected) immediately following.
Bit A1 Bit A0
0 0
0 1
1 0
1 1
Load and Store Instructions
Register
x x x x x x x
DMA Command (DCMD)
value. This is either the actual memory
Number of Bytes Allowed to Load and Store
One, two, three or four
One, two, or three
One or two
One
x x x x x x x
and DMA Byte
Data Structure
0
x x x x
[31:0]
DMA
5-35