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LSI53C875A
Technical manual
Maximum Synchronous Offset - LSI LSI53C875A Technical Manual
Pci to ultra scsi controller
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4-34
Table 4.5
Maximum Synchronous Offset
MO4
MO3
MO2
0
0
0
0
0
0
0
0
0
0
0
0
0
0
1
0
0
1
0
0
1
0
0
1
0
1
0
0
1
0
0
1
0
0
1
0
0
1
1
0
1
1
0
1
1
0
1
1
1
0
0
1
0
0
1
0
0
1
0
0
1
0
1
1
0
1
1
0
1
1
0
1
1
1
0
1
1
0
1
1
0
1
1
0
1
1
1
1
1
1
1
1
1
1
1
1
Registers
MO1
MO0
Synchronous Offset
0
0
0-Asynchronous
0
1
1
0
1
1
0
0
0
1
1
0
1
1
0
0
0
1
1
0
1
1
0
0
0
1
1
0
1
1
0
0
0
1
1
0
1
1
0
0
0
1
1
0
1
1
0
0
0
1
1
0
1
1
0
0
0
1
1
0
1
1
1
2
3
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5
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Bidirectional Signals—Mad[7:0], Mas/[1:0], Mce/, Moe Mwe/
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