Bit Address Operating Register/Scripts Ram Write - LSI LSI53C875A Technical Manual

Table 6.20

64-Bit Address Operating Register/SCRIPTS RAM Write

Symbol Parameter
t Shared signal input setup time
1
t Shared signal input hold time
2
t CLK to shared signal output valid
3
Figure 6.14 64-Bit Address Operating Register/SCRIPTS RAM Write
CLK
(Driven by System)
FRAME/
(Driven by Master)
AD
(Driven by Master)
C_BE/
(Driven by Master)
PAR
(Driven by Master)
IRDY/
(Driven by Master)
TRDY/
(Driven by LSI53C875A)
STOP/
(Driven by LSI53C875A)
DEVSEL/
(Driven by LSI53C875A)
6-18
t
1
t t
1
Addr Addr
Lo Hi
t
2
t
1
Dual Bus
Addr CMD
t
2
t
1
In
Electrical Specifications
1
Data In
t
1
Byte Enable
In
t
2
t
1
t
3
Min Max
7 –
0 –
– 11
t
2
t
2
t
2
t
1
In
t
2
t
3
Unit
ns
ns
ns
t
2
t
2