Target Timing; Pci Configuration Register Read - LSI LSI53C875A Technical Manual

6.4.1 Target Timing

Table 6.15

PCI Configuration Register Read

Symbol Parameter
t Shared signal input setup time
1
t Shared signal input hold time
2
t CLK to shared signal output valid
3
Figure 6.9 PCI Configuration Register Read
CLK
(Driven by System)
FRAME/
(Driven by System)
AD
(Driven by Master-Addr;
LSI53C875A-Data)
C_BE/
(Driven by Master
PAR
(Driven by Master-Addr;
LSI53C875A-Data)
IRDY/
(Driven by Master)
TRDY/
(Driven by LSI53C875A)
STOP/
(Driven by LSI53C875A)
DEVSEL/
(Driven by LSI53C875A)
IDSEL
(Driven by Master)
The tables and figures in this section describe target timings.
t
1
t
2
t
1
Addr
In
t
2
t
1
CMD
)
t
2
t
1
t
1
t
2
PCI and External Memory Interface Timing Diagrams
t
3
Data Out
Byte Enable
t
1
In
t
2
t
3
Min Max
7 –
0 –
– 11
t
2
t3
Out
t
2
t
3
Unit
ns
ns
ns
6-13