Bus Cycle Waveforms - Intel 80C186EA Preliminary Information

80C186EA 80C188EA 80L186EA 80L188EA

BUS CYCLE WAVEFORMS

Figures 17 through 23 present the various bus cycles that are generated by the processor What is shown in
the figure is the relationship of the various bus signals to CLKOUT These figures along with the information
present in AC Specifications allow the user to determine all the critical timing analysis needed for a given
application
NOTES
1 During the data phase of the bus cycle A19 S6 is driven high for a DMA or refresh cycle
2 Pin names in parentheses apply to the 80C188EA
Figure 17 Read Fetch and Refresh Cycle Waveform
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