Dram Latency; Figure 3-2. Memory Block Diagram; Table 3-5. Mpc 60X Bus To Dram Access Timing Using 60Ns Page Devices - Motorola MVME2300 Series Installation And Use Manual

Functional Description
3

DRAM Latency

Table 3-5. MPC 60x Bus to DRAM Access Timing using 60ns Page Devices

Access Type
4-Beat Read after Idle
(Quad-word aligned)
4-Beat Read after Idle
(Quad-word misaligned)
4-Beat Read after 4-Beat Read
(Quad-word aligned)
4-Beat Read after 4-Beat Read
(misaligned)
4-Beat Write after Idle
3-8
Memory Controller
Falcon Chipset
Buffers

Figure 3-2. Memory Block Diagram

The ECC memory access latency times for 60ns, fast page DRAMs are
shown in the following table.
Clock Periods Required for:
1st Beat
9
9
7/3
6/2
4
ECC DRAM
16M to 128M
FLASH
3M to 5M
2nd Beat 3rd Beat
1 2
3 1
1
1 2
1
3 1
1 1
Computer Group Literature Center Web Site
Buffers
Buffers
Total
Clocks
4th Beat
1 13
1 14
1 11/7
1 11/7
7
1