Hardware Interrupts - Intel ARM Cortex-A9 Introduction Manual

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NTRODUCTION TO THE

11.2 Hardware Interrupts

Hardware interrupts can be raised by external sources, such as I/O devices, by asserting one of the processor's
interrupt-request inputs, IRQ or FIQ. When the processor receives a hardware interrupt request, it enters the corre-
sponding exception mode to service the interrupt. It also saves the contents of PC and CPSR.
The saved contents of the PC are supposed to be the return address. However, this is not the case with the ARM
Cortex-A9 processor. This processor prefetches instructions for execution. While the current instruction is being
executed, the next instruction is prefetched and its processing is started. This means that the Program Counter
points to the instruction after the prefetched one. Namely, the updated contents of PC are the address of the current
instruction plus 8. Since the interrupt is serviced upon completion of the current instruction, the next prefetched
instruction is discarded and it must be executed upon return from the interrupt. Therefore, the address saved in the
link register must be decremented by 4 prior to returning to the interrupted program. This can be done by having
as the last instruction in the exception-service routine. Note that the suffix S causes a proper return to the interrupted
program, as explained above.
11.2.1 IRQ Interrupts
Upon accepting an IRQ interrupt request, the processor saves the contents of CPSR in the SPSR_irq register, and it
saves the contents of PC in the link register LR_irq. It also sets the mode bits in CPSR to denote the IRQ exception
mode, and it sets the I bit to 1 to disable further IRQ interrupts. Then, it executes the instruction at location 0x018
of the exception vector table, which has to cause a branch that leads to the IRQ exception-service routine.
The return from the exception-service routine should be performed with the instruction
11.2.2 FIQ Interrupts
An FIQ interrupt request is raised by a device that needs fast response. Upon accepting the request, the processor
saves the contents of CPSR in the SPSR_fiq register, and it saves the contents of PC in the link register LR_fiq. It
also sets the mode bits in CPSR to denote the FIQ exception mode, and it sets the F and I bits to 1 to disable further
interrupts. Then, it executes the instruction at location 0x01C of the exception vector table. Since this is the last
location in the exception vector table, it can actually hold the first instruction of the FIQ exception-service routine
(instead of an instruction that causes a branch to the FIQ exception-service routine), which speeds up the response
to the FIQ request.
In the FIQ mode there are five additional banked registers, R8_fiq to R12_fiq, which means that the exception-service
routine can use these registers without first having to save the contents of R8 to R12 on the stack. This leads to a
faster response.
The return from the exception-service routine should be performed with the instruction
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SUBS PC, LR, #4
SUBS PC, LR, #4
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