Hardware-Implementation-Dependent Register 2 (Hid2) - IBM PowerPC 750GX User Manual

2.1.2.4 Hardware-Implementation-Dependent Register 2 (HID2)

The Hardware-Implementation-Dependent Register 2 (HID2) enables parity. The status bits (25:27) are set
when a parity error is detected and cleared by writing '0' to each bit. See the IBM PowerPC 750GX RISC
Microprocessor Datasheet for details.
HID2 can be accessed with mtspr and mfspr using SPR 1016.
Reserved
0 1 2 3 4 5 6
Bits Field Name
0:2 Reserved
3 STMUMD
4:19 Reserved
20 FICBP
21 FITBP
22 FDCBP
23 FDTBP
24 FL2TBP
25 ICPS
26 DCPS
27 L2PS
28 Reserved
29 ICPE
30 DCPE
31 L2PE
1. Reserved. Used as factory test bits. Do not change from their power-up state unless indicated to do so.
gx_02.fm.(1.2)
March 27, 2006
Reserved
7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31
Reserved
Disable store miss-under-miss processing (changes the allowed outstanding store
misses from two to one.
Reserved
Force instruction-cache bad parity.
Force instruction-tag bad parity.
Force data-cache bad parity.
Force data-tag bad parity.
Force L2-tag bad parity.
L1 instruction-cache/instruction-tag parity error status/mask.
L1 data-cache/data-tag parity error status/mask.
L2 tag parity error status/mask.
Reserved.
Enable L1 instruction-cache/instruction-tag parity checking.
Enable L1 data-cache/data-tag parity checking.
Enable L2 tag parity checking.
IBM PowerPC 750GX and 750GL RISC Microprocessor
Description
User's Manual
Notes
1
1
1
Programming Model
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