Table 9-1. Interpretation Of Lru Bits - IBM PowerPC 750GX User Manual

User's Manual
IBM PowerPC 750GX and 750GL RISC Microprocessor
If multiple read requests from the L1 caches are pending, the L2 cache can perform hit-under-miss opera-
tions, supplying the available instruction or data while a bus transaction for previous L2 cache misses is being
performed. The L2 cache also supports miss-under-miss operation. Up to four outstanding misses are
supported: one miss from the instruction cache and three from the data cache, or four data-cache misses.
Requests that hit will be serviced even while misses are in progress on the bus.
All requests to the L2 cache that are marked cacheable (even if the respective L1 cache is disabled or locked)
cause tag lookup and will be serviced if the instructions or data are in the L2 cache. Burst and single-beat
read requests from the L1 caches that hit in the L2 cache are forwarded to the L1 caches as instructions or
data, and the L2 LRU bit for that tag is updated. Burst writes from the L1 data cache due to a castout or
replacement copyback are written only to the L2 cache, and the L2 cache sector is marked modified.
If the L2 cache is configured as write-through, the L2 sector is marked unmodified, and the write is forwarded
to the 60x bus. If the L1 castout requires a new L2 tag entry to be allocated and the current tag is marked
modified, any modified sectors of the tag to be replaced are cast out of the L2 cache to the 60x bus.
Single-beat read requests from the L1 caches that miss in the L2 cache do not cause any state changes in
the L2 cache and are forwarded on the 60x bus interface. Cacheable single-beat store requests marked
copy-back that hit in the L2 cache are allowed to update the L2 cache sector, but do not cause L2-cache
sector allocation or deallocation. Cacheable, single-beat store requests that miss in the L2 cache are
forwarded to the 60x bus. Single-beat store requests marked write-through (through address translation or
through the configuration of L2CR[WT]) are written to the L2 cache if they hit, and are written to the 60x bus
independent of the L2 hit/miss status. If the store hits in the L2 cache, the modified/unmodified status of the
tag remains unchanged. All requests to the L2 cache that are marked cache-inhibited by address translation,
through either the memory management unit (MMU) or by the default write/cache inhibit/memory coher-
ence/guarded storage (WIMG) configuration, bypass the L2 cache and do not cause any L2-cache tag state
change.
The 750GX microprocessor 4-way set-associative L2 cache uses a 3-bit per set, pseudo-LRU replacement
algorithm. Bit 0 is the global LRU bit, which indicates that the LRU way is in the lower (0 or 1) or upper (2 or 3)
ways. Bit 1 is the lower LRU bit, which indicates that the LRU way is either way 0 or way 1. Bit 2 is the upper
LRU bit, which indicates that the LRU way is either way 2 or way 3. Together, the three bits represent a partial
ordering of the four ways, such that the LRU and most recently used (MRU) ways are identified, but the other
two ways are not ordered with respect to each other. Table 9-1 shows the interpretation of the three LRU bits
in the absence of any cache locking.

Table 9-1. Interpretation of LRU Bits

LRU Bits
000
001
010
011
100
110
101
111
L2 Cache
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LRU Way
0
0
1
1
2
2
3
3
MRU Way
3
2
3
2
1
0
1
0
gx_09.fm.(1.2)
March 27, 2006