Table 9-2. Modification Of Lru Bits; Table 9-3. Effect Of Locked Ways On Lru Interpretation - IBM PowerPC 750GX User Manual

Whenever a way in the set is referenced, the LRU bits are updated. The new value of the LRU bits depends
on the old value, which way is currently being accessed, and whether the operation is an invalidation or a
load/store. Table 9-2 shows the new value of the LRU bits for the various combinations of these variables. An
'x' indicates don't care, while a '-' indicates no change from previous value.

Table 9-2. Modification of LRU Bits

Old LRU
00x
01x
1x0
1x1
xxx
xxx
xxx
xxx
xxx
xxx
xxx
xxx
The 4-way set-associative L2 cache can be locked by way as described below. The determination of the new
LRU value does not depend on the locked status of the ways. However, the interpretation of the LRU bits
shown in Table 9-2 does change when one or more ways of the cache are locked.
Any combination of ways can be locked. The effect of locking on the replacement algorithm is that the least
recently used of the unlocked ways is chosen for replacement. Table 9-3 shows the interpretation of the LRU
bits in the presence of one or two locked ways. If three ways are locked, the unlocked way is always replaced,
and if all four ways are locked, no replacement takes place. In Table 9-3, bit zero of the lock bits controls
whether way 0 is locked, bit one controls whether way 1 is locked, and so forth.

Table 9-3. Effect of Locked Ways on LRU Interpretation

LRU Bits
00x
00x
000
001
01x
01x
010
011
1x0
1x0
100
gx_09.fm.(1.2)
March 27, 2006
IBM PowerPC 750GX and 750GL RISC Microprocessor
Hit Way
none
none
none
none
0
1
2
3
0
1
2
3
(Page 1 of 2)
Lock Bits
0xxx
10xx
110x
11x0
x0xx
01xx
110x
11x0
xx0x
xx10
0x11
Invalidate
x
x
x
x
0
0
0
0
1
1
1
1
LRU Way
User's Manual
New LRU
11-
10-
0-1
0-0
11-
10-
0-1
0-0
00-
01-
1-0
1-1
0
1
2
3
1
0
2
3
2
3
0
L2 Cache
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