Machine-Check Interrupt (Mcp)-Input; Checkstop Input (Ckstp_In)-Input; Checkstop Output (Ckstp_Out)-Output - IBM PowerPC 750GX User Manual

7.2.9.3 Machine-Check Interrupt (MCP)—Input
State Asserted
Negated
Timing Assertion
Negation
7.2.9.4 Checkstop Input (CKSTP_IN)—Input
State Asserted
Negated
Timing Assertion
Negation
7.2.9.5 Checkstop Output (CKSTP_OUT)—Output
Note that the CKSTP_OUT signal is an open-drain type output, and requires an external pull-up resistor (for
example, 10 kΩ to V ) to assure proper deassertion of the CKSTP_OUT signal.
DD
State Asserted
Negated
Timing Assertion
High
Impedance
Note: CKSTP_OUT operates as an open-drain output. It will either be in the asserted or
high-impedance state.
gx_07.fm.(1.2)
March 27, 2006
The 750GX initiates a machine-check interrupt operation if MSR[ME] and
HID0[EMCP] are set. If MSR[ME] is cleared and HID0[EMCP] is set, the
750GX must terminate operation by internally gating off all clocks, and
releasing all outputs (except CKSTP_OUT) to the high-impedance state. If
HID0[EMCP] is cleared, the 750GX ignores the interrupt condition. The MCP
signal must be held asserted for two bus clock cycles.
Indicates that normal operation should proceed.
May occur at any time and may be asserted asynchronously to the input
clocks. The MCP input is negative edge-sensitive.
May be negated two bus cycles after assertion.
Indicates that the 750GX must enter the checkstop state and terminate oper-
ation. The 750GX will internally gate off all clocks and remain in this state
while CKSTP_IN is asserted. The 750GX will also release all outputs (except
CKSTP_OUT) to the high-impedance state. CKSTP_IN is not maskable.
Once CKSTP_IN has been asserted it must remain asserted until the system
has been reset.
Indicates that normal operation should proceed.
May occur at any time and may be asserted asynchronously to the input
clocks.
May occur any time after the CKSTP_IN output has been asserted.
Indicates that a checkstop condition has been detected, and the processor
has ceased operation.
Indicates that the processor is operating normally.
Might occur at any time and can be asserted asynchronously to input clocks.
Requires HRESET.
IBM PowerPC 750GX and 750GL RISC Microprocessor
User's Manual
Signal Descriptions
Page 271 of 377