Enabling And Disabling Exceptions; Steps For Exception Processing; Table 4-4. Ieee Floating-Point Exception Mode Bits - IBM PowerPC 750GX User Manual

User's Manual
IBM PowerPC 750GX and GL RISC Microprocessor

Table 4-4. IEEE Floating-Point Exception Mode Bits

FE0 FE1 Mode
0 0 Floating-point exceptions disabled.
0 1 Imprecise nonrecoverable. For this setting, the 750GX operates in floating-point precise mode.
1 0 Imprecise recoverable. For this setting, the 750GX operates in floating-point precise mode.
1 1 Floating-point precise mode.

4.3.4 Enabling and Disabling Exceptions

When a condition exists that might cause an exception to be generated, it must be determined whether the
exception is enabled for that condition.
• IEEE floating-point enabled exceptions (a type of program exception) are ignored when both MSR[FE0]
and MSR[FE1] are cleared. If either bit is set, all IEEE enabled floating-point exceptions are taken and
cause a program exception.
• Asynchronous, maskable exceptions (such as the external and decrementer interrupts) are enabled by
setting MSR[EE]. When MSR[EE] = 0, recognition of these exception conditions is delayed. MSR[EE] is
cleared automatically when an exception is taken, to delay recognition of conditions causing those excep-
tions.
• A machine-check exception can occur only if the machine-check enable bit, MSR[ME], is set. If MSR[ME]
is cleared, the processor goes directly into checkstop state when a machine-check exception condition
occurs. Individual machine-check exceptions can be enabled and disabled through bits in the HID0 Reg-
ister, which is described in Table 4-8 on page 167.
• System reset exceptions cannot be masked.

4.3.5 Steps for Exception Processing

After it is determined that the exception can be taken (by confirming that any instruction-caused exceptions
occurring earlier in the instruction stream have been handled, and by confirming that the exception is enabled
for the exception condition), the processor does the following:
1. SRR0 is loaded with an instruction address that depends on the type of exception. Normally, this is the
instruction that would have completed next had the exception not been taken. See the individual excep-
tion description for details about how this register is used for specific exceptions.
2. SRR1[1:4, 10:15] are loaded with information specific to the exception type.
3. SRR1[5:9, 16:31] are loaded with a copy of the corresponding MSR bits. Depending on the implementa-
tion, reserved bits might not be copied.
4. The MSR is set as described in Section 4.3.6. The new values take effect as the first instruction of the
exception-handler routine is fetched.
5. Note that MSR[IR] and MSR[DR] are cleared for all exception types. Therefore, address translation is dis-
abled for both instruction fetches and data accesses beginning with the first instruction of the exception-
handler routine.
6. Instruction fetch and execution resumes, using the new MSR value, at a location specific to the exception
type. The location is determined by adding the exception's vector (see Table 4-2 on page 152) to the
base address determined by MSR[IP]. If IP is cleared, exceptions are vectored to the physical address
Exceptions
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March 27, 2006