Cache Miss - IBM PowerPC 750GX User Manual

User's Manual
IBM PowerPC 750GX and 750GL RISC Microprocessor
10. In cycle 9, instruction 11 completes, instruction 12 continues through the FPU pipeline, and instructions
13 and 14 are dispatched. One new instruction, 18, can be fetched on this cycle because the instruction
queue had one opening on the previous clock cycle.

6.3.2.3 Cache Miss

Figure 6-6 on page 223 shows an instruction fetch that misses both the L1 cache and L2 cache. A
processor/bus clock ratio of 1:2 is used. The same instruction sequence is used as in Section 6.3.2.2, Cache
Hit. However, in this example, the branch target instruction is not in either the L1 or L2 cache.
A cache miss extends the latency of the fetch stage, so, in this example, the fetch stage shown represents
not only the time the instruction spends in the IQ, but the time required for the instruction to be loaded from
system memory, beginning in clock cycle 2.
During clock cycle 3, the target instruction for the b instruction is not in the BTIC, the instruction cache, or the
L2 cache; therefore, a memory access must occur. During clock cycle 5, the address of the block of instruc-
tions is sent to the system bus. During clock cycle 7, two instructions (64 bits) are returned from memory on
the first beat and are forwarded both to the cache and the instruction fetcher.
Instruction Timing
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gx_06.fm.(1.2)
March 27, 2006