I/O Voltage Select Signals; Test Interface Signals; Ieee 1149.1A-1993 Interface Description; Lssd_Mode - IBM PowerPC 750GX User Manual

7.2.13 I/O Voltage Select Signals

Table 7-7 shows the settings for the I/O voltage signals.

Table 7-7. Bus Voltage Selection Settings

Voltage Selection
Reserved
1.8 V
2.5 V
3.3 V

7.2.14 Test Interface Signals

The processor provides two sets of pins for controlling JTAG and level-sensitive scan design (LSSD) testing.

7.2.14.1 IEEE 1149.1a-1993 Interface Description

The 750GX has five dedicated JTAG signals, which are described in Table 7-8. The test data input (TDI) and
test data output (TDO) scan ports are used to scan instructions, as well as data into the various scan regis-
ters for JTAG operations. The scan operation is controlled by the test access port (TAP) controller, which in
turn is controlled by the test mode select (TMS) input sequence. The scan data is latched in at the rising edge
of the test clock (TCK). Test reset (TRST) is a JTAG optional signal, which is used to reset the TAP controller
asynchronously. The TRST signal assures that the JTAG logic does not interfere with the normal operation of
the chip, and must be asserted and deasserted coincident with the assertion of the HRESET signal.

Table 7-8. IEEE Interface Pin Descriptions

Signal Name Input/Output
TDI Input
TDO Output
TMS Input
TCK Input
TRST Input

7.2.14.2 LSSD_MODE

State Asserted
Timing Assertion/
Negation
gx_07.fm.(1.2)
March 27, 2006
OV Select #1
DD
BVSEL
0
0
1
1
Weak Pullup Provided
Yes
No
Yes
No
Yes
LSSD test enable. The LSSD test enable signal is an input-only signal.
Must be set high by the system during normal operation.
IBM PowerPC 750GX and 750GL RISC Microprocessor
IEEE 1149.1a-1993 Function
Serial scan input signal
Serial scan output signal
TAP controller mode signal
Scan clock
TAP controller reset
User's Manual
OV Select #2
DD
L1TSTCLK
0
1
1
0
Timing Comments
Asserted/Negated—Not used
during normal operation. TMS,
TDI, and TRST have internal
pullups provided; TCK does not.
For normal operation, TMS and
TDI may be left unconnected,
TCK must be set high or low,
and TRST must be asserted
sometime during power-up for
JTAG logic initialization.
Signal Descriptions
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