IBM PowerPC 750GX User Manual page 149

Table 3-7. MEI State Transitions
Cache
Operation
Operation
tlbie TLB invalidate
Synchroniza-
sync
tion
Note: Single-beat writes are not snooped in the write queue.
gx_03.fm.(1.2)
March 27, 2006
(Page 3 of 3)
Current
Bus
WIM Cache
Sync
State
No xxx x
No xxx x
IBM PowerPC 750GX and 750GL RISC Microprocessor
Next
Cache Cache Actions
State
Pass TLBI.
x
No action.
Pass sync.
x
No action.
Instruction-Cache and Data-Cache Operation
User's Manual
Bus Operation
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