Table of Contents
Advertisement
Table 5-8. Model for Guaranteed R and C Bit Settings
Priority
Out-of-order store operation. Required by the sequential
execution model in the absence of system-caused or
4
imprecise exceptions, or of floating-point assist exception
for instructions that would cause no other kind of precise
exception.
5
All other out-of-order store operations
6
Zero-length load (lswx)
7
Zero-length store (stswx)
8
Store conditional (stwcx.) that does not store
9
In-order instruction fetch
10
Load instruction or eciwx
11
Store instruction, ecowx, or dcbz instruction
Instruction Cache Block Invalidate (icbi), dcbt, or dcbtst
12
instruction
Data Cache Block Store (dcbst) or Data Cache Block
13
Flush (dcbf) instruction
14
Data Cache Block Invalidate (dcbi) instruction
Note:
1
If C is set, R is guaranteed to be set also.
For more information, see "Page History Recording" in Chapter 7, "Memory Management," of the PowerPC
Microprocessor Family: The Programming Environments Manual.
5.4.2 Page Memory Protection
The 750GX implements page memory protection as it is defined in Chapter 7, "Memory Management," in the
PowerPC Microprocessor Family: The Programming Environments Manual.
5.4.3 TLB Description
The 750GX implements separate 128-entry data and instruction TLBs to maximize performance. This section
describes the hardware resources provided in the 750GX to facilitate page-address translation. Note that the
architecture does not specify the hardware implementation of the MMU, and while this description applies to
the 750GX, it does not necessarily apply to other PowerPC processors.
5.4.3.1 TLB Organization
Because the 750GX has two MMUs (IMMU and DMMU) that operate in parallel, some of the MMU resources
are shared, and some are actually duplicated (shadowed) in each MMU to maximize performance. For
example, although the architecture defines a single set of Segment Registers for the MMU, the 750GX main-
tains two identical sets of Segment Registers, one for the IMMU and one for the DMMU. When an instruction
that updates the Segment Register executes, the 750GX automatically updates both sets.
gx_05.fm.(1.2)
March 27, 2006
Scenario
IBM PowerPC 750GX and 750GL RISC Microprocessor
(Page 2 of 2)
Causes Setting of R Bit
OEA
750GX
1
Maybe
No
1
Maybe
No
Maybe
No
1
Maybe
No
1
Maybe
Yes
Yes
Yes
Yes
Yes
Yes
Yes
Maybe
No
Maybe
Yes
1
Maybe
Yes
User's Manual
Causes Setting of C Bit
OEA
750GX
No
No
1
Maybe
No
No
No
1
Maybe
No
1
Maybe
Yes
No
No
No
No
Yes
Yes
No
No
No
No
1
Maybe
Yes
Memory Management
Page 199 of 377
Hide quick links:
Advertisement
Table of Contents
