Table 2-9. Integer Logical Instructions - IBM PowerPC 750GX User Manual

User's Manual
IBM PowerPC 750GX and 750GL RISC Microprocessor
Integer Logical Instructions
The logical instructions shown in Table 2-9 on page 94 perform bit-parallel operations on the specified oper-
ands. Logical instructions with CR updating enabled (uses dot suffix) and the AND Immediate (andi.) and
AND Immediate Shifted (andis.) instructions set the CR[CR0] field to characterize the result of the logical
operation. Logical instructions do not affect XER[SO], XER[OV], or XER[CA].
See Appendix F, "Simplified Mnemonics," in the PowerPC Microprocessor Family: The Programming Envi-
ronments Manual for simplified mnemonic examples for integer logical operations.

Table 2-9. Integer Logical Instructions

Name
AND Immediate
AND Immediate Shifted
OR Immediate
OR Immediate Shifted
XOR Immediate
XOR Immediate Shifted
AND
OR
XOR
NAND
NOR
Equivalent
AND with Complement
OR with Complement
Extend Sign Byte
Extend Sign Half Word
Count Leading Zeros Word
Integer Rotate Instructions
Rotation operations are performed on data from a GPR, and the result, or a portion of the result, is returned to
a GPR. See Appendix F, "Simplified Mnemonics," in the PowerPC Microprocessor Family: The Programming
Environments Manual for a complete list of simplified mnemonics that allows simpler coding of often-used
functions such as clearing the leftmost or rightmost bits of a register, left justifying or right justifying an arbi-
trary field, and simple rotates and shifts.
Integer rotate instructions rotate the contents of a register. The result of the rotation is either inserted into the
target register under control of a mask (if a mask bit is 1, the associated bit of the rotated data is placed into
the target register, and if the mask bit is 0, the associated bit in the target register is unchanged), or ANDed
with a mask before being placed into the target register.
Programming Model
Page 94 of 377
Mnemonic Syntax
andi. rA,rS,UIMM
andis. rA,rS,UIMM
ori rA,rS,UIMM
oris rA,rS,UIMM
xori rA,rS,UIMM
xoris rA,rS,UIMM
and (and.) rA,rS,rB
or (or.) rA,rS,rB
xor (xor.) rA,rS,rB
nand (nand.) rA,rS,rB
nor (nor.) rA,rS,rB
eqv (eqv.) rA,rS,rB
andc (andc.) rA,rS,rB
orc (orc.) rA,rS,rB
extsb (extsb.) rA,rS
extsh (extsh.) rA,rS
cntlzw (cntlzw.) rA,rS
Implementation Notes
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The PowerPC Architecture defines ori r0,r0,0 as the pre-
ferred form for the no-op instruction. The dispatcher dis-
cards this instruction (except for pending trace or
breakpoint exceptions).
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gx_02.fm.(1.2)
March 27, 2006