Table 2-19. Integer Store Instructions - IBM PowerPC 750GX User Manual

Integer Store Instructions
For integer store instructions, the contents of the source register (rS) are stored into the byte, half word, or
word in memory addressed by the EA. Many store instructions have an update form, in which rA is updated
with the EA. For these forms, the following rules apply:
• If rA ≠ 0, the effective address is placed into rA.
• If rS = rA, the contents of register rS are copied to the target memory element, and then the generated
EA is placed into rA (rS).
The PowerPC Architecture defines store with update instructions with rA = 0 as an invalid form. In addition, it
defines integer store instructions with the CR update option enabled (Rc field, bit 31, in the instruction
encoding = 1) to be an invalid form.
Table 2-19 summarizes the integer store instructions.

Table 2-19. Integer Store Instructions

Name
Store Byte
Store Byte Indexed
Store Byte with Update
Store Byte with Update Indexed
Store Half Word
Store Half Word Indexed
Store Half Word with Update
Store Half Word with Update Indexed
Store Word
Store Word Indexed
Store Word with Update
Store Word with Update Indexed
Integer Store Gathering
The 750GX performs store gathering for write-through accesses to nonguarded space or to cache-inhibited
stores to nonguarded space if the stores are 4 bytes and they are word-aligned. These stores are combined
in the load/store unit (LSU) to form a double word that is sent out on the 60x bus as a single-beat operation.
Stores are gathered only if successive, eligible stores are queued and pending. Store gathering takes place
regardless of address order or endian mode. The store-gathering feature is enabled by setting the HID0[SGE]
bit (bit 24).
Store gathering is not done for:
• Cacheable stores
• Stores to guarded cache-inhibited or write-through space
• Byte-reverse store
• Store Word Conditional Indexed (stwcx.) and External Control Out Word Indexed (ecowx) accesses
• Floating-point stores
gx_02.fm.(1.2)
March 27, 2006
IBM PowerPC 750GX and 750GL RISC Microprocessor
Mnemonic
stb
stbx
stbu
stbux
sth
sthx
sthu
sthux
stw
stwx
stwu
stwux
User's Manual
Syntax
rS,d(rA)
rS,rA,rB
rS,d(rA)
rS,rA,rB
rS,d(rA)
rS,rA,rB
rS,d(rA)
rS,rA,rB
rS,d(rA)
rS,rA,rB
rS,d(rA)
rS,rA,rB
Programming Model
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