Figure 6-4. Instruction Flow Diagram - IBM PowerPC 750GX User Manual

User's Manual
IBM PowerPC 750GX and 750GL RISC Microprocessor

Figure 6-4. Instruction Flow Diagram

IQ5 IQ4
Completion Queue
Assignment
Reservation
Stations
Store Queue
Instruction Timing
Page 218 of 377
IQ3 IQ2 IQ1
Branch
Processing Unit
LSU
CQ5 CQ4
Fetch
(Maximum of four instructions per clock cycle)
Instruction Queue
IQ0
(In program order)
Dispatch
(Maximum of two instructions per clock cycle;
one instruction per unit)
FPU
IU1
CQ3 CQ2
Complete (Retire)
IU2
CQ1 CQ0
Completion Queue
(In program order)
gx_06.fm.(1.2)
March 27, 2006
SRU