Parity Control And Status; Enabling Parity Error Detection; Parity Errors - IBM PowerPC 750GX User Manual

User's Manual
IBM PowerPC 750GX and 750GL RISC Microprocessor

11.10.1 Parity Control and Status

Parity is enabled with the Hardware-Implementation-Dependent Register 2 (HID2).
For a diagram of this register and a description of its fields, see Hardware-Implementation-Dependent
Register 2 (HID2) on page 71.
HID2 SPR number is 1016 decimal, (spr[5-9] = 11111, spr[0-4] = 11000).
The status bits (25:27) are set when a parity error is detected and cleared when the HID2 Register is written.

11.10.2 Enabling Parity Error Detection

Parity error detection can be enabled at any time by setting the parity enable bits for the desired arrays in the
HID2 Register (ICPE, DCPE, and L2PE for the ICache/ITag, DCache/DTag, and L2Tag respectively). Parity
errors are reported with the parity status bits in the HID2 Register (ICPS, DCPS, and L2PS for ICache/ITag,
DCache/DTag, and L2Tag respectively). The parity status bits are read only and are automatically cleared
each time the HID2 register is written.

11.10.3 Parity Errors

All parity errors will cause a machine-check interrupt. Since this is an imprecise interrupt, recovery is not
possible. To determine the cause of the machine check, the software must have set the machine-check
enable [ME] bit of the MSR and have an interrupt handler located at 0x00200. This handler can read the
parity status bits in HID2 for display or checking. If the cause of the machine check is found to be a parity
error then after the handler has completed an HRESET must be initiated.
Performance Monitor and System Related Features gx_11.fm.(1.2)
Page 364 of 377 March 27, 2006