Table 6-8. Floating-Point Instructions - IBM PowerPC 750GX User Manual

User's Manual
IBM PowerPC 750GX and 750GL RISC Microprocessor
Table 6-7. Integer Instructions
Instruction Mnemonic
Subtract From Carrying subfc[o][.]
Subtract From
subfe[o][.]
Extended
Subtract From
Immediate Carrying
Subtract From Minus
subfme[o][.]
One Extended
Subtract From Zero
subfze[o][.]
Extended
Subtract From
Trap Word
Trap Word Immediate
XOR Immediate
XOR Immediate Shifted
XOR
Table 6-8 shows latencies for floating-point instructions. Pipelined floating-point instructions are shown with
the number of clocks in each pipeline stage separated by dashes. Floating-point instructions with a single
entry in the cycles column are not pipelined. When the FPU executes these nonpipelined instructions, it
remains busy for the full duration of the instruction execution and is not available for subsequent instructions.

Table 6-8. Floating-Point Instructions

Instruction Mnemonic
Floating Absolute Value
Floating Add Single fadds[.]
Floating Add
Floating Compare
Ordered
Floating Compare
Unordered
Floating Convert To
Integer Word with fctiwz[.]
Round toward Zero
Floating Convert To
Integer Word
Floating Divide Single
Floating Divide
Floating Multiply-Add
fmadds[.]
Single
Floating Multiply-Add fmadd[.]
Floating Move Register
Instruction Timing
Page 242 of 377
(Page 3 of 3)
Primary Extended
Opcode
31
31
subfic 8
31
31
subf[.] 31
tw 31
twi 3
xori 26
xoris 27
xor[.] 31
(Page 1 of 2)
Primary Extended
Opcode
fabs[.] 63
59
fadd[.] 63
fcmpo 63
fcmpu 63
63
fctiw[.] 63
fdivs[.] 59
fdiv[.] 63
59
63
fmr[.] 63
Unit
Opcode
8 IU1/IU2
136 IU1/IU2
— IU1/IU2
232 IU1/IU2
200 IU1/IU2
40 IU1/IU2
4 IU1/IU2
— IU1/IU2
— IU1/IU2
— IU1/IU2
316 IU1/IU2
Unit
Opcode
264 FPU
21 FPU
21 FPU
32 FPU
0 FPU
15 FPU
14 FPU
18 FPU
18 FPU
29 FPU
29 FPU
72 FPU
Cycles Serialization
1 —
1 Execution
1 —
1 Execution
1 Execution
1 —
2 —
2 —
1 —
1 —
1 —
Cycles Serialization
1-1-1 —
1-1-1 —
1-1-1 —
1-1-1 —
1-1-1 —
1-1-1 —
1-1-1 —
17 —
31 —
1-1-1 —
2-1-1 —
1-1-1 —
March 27, 2006
gx_06.fm.(1.2)