Instruction Latency Summary; Table 6-4. Branch Instructions; Table 6-5. System-Register Instructions - IBM PowerPC 750GX User Manual

User's Manual
IBM PowerPC 750GX and 750GL RISC Microprocessor
• Requirements for completing an instruction from CQ1:
– Instruction in CQ0 must complete in same cycle.
– Instruction in CQ1 must be finished.
– Instruction in CQ1 must not follow an unresolved predicted branch.
– Instruction in CQ1 must not cause an exception.
– Instruction in CQ1 must be an integer or load instruction.
– Number of CR updates from both CQ0 and CQ1 must not exceed two.
– Number of GPR updates from both CQ0 and CQ1 must not exceed two.
– Number of FPR updates from both CQ0 and CQ1 must not exceed two.

6.7 Instruction Latency Summary

Table 6-4 through Table 6-9 list the latencies associated with instructions executed by each execution unit.
Table 6-4 describes branch instruction latencies.

Table 6-4. Branch Instructions

Instruction Mnemonic
Branch
Branch Conditional
Branch Conditional to
Count Register
Branch Conditional to
Link Register
Table 6-5 lists system-register instruction latencies.

Table 6-5. System-Register Instructions

Instruction Mnemonic
Enforce In-Order
Execution of I/O
Instruction Synchronize
Move-from Machine
State Register
1. This 3-cycle operation assumes no pending stores in the store queue. If there are pending stores, the sync completes after the
stores complete to memory. If broadcast is enabled on the 60x bus, sync completes only after a successful broadcast.
2. tlbsync is dispatched only to the completion buffer (not to any execution unit) and is marked finished as it is dispatched. Upon
retirement, it waits for an external TLB Invalidate Synchronize (TLBISYNC) signal to be asserted. In most systems, TLBISYNC is
always asserted so the instruction is a no-op.
Instruction Timing
Page 238 of 377
Primary Extended
Opcode
b[l][a] 18
bc[l][a] 16
bcctr[l] 19
bclr[l] 19
(Page 1 of 2)
Primary Extended
Opcode
eieio 31
isync 19
mfmsr 31
Opcode
—
—
Unless these instructions update either the CTR or the LR,
branch operations are folded if they are either taken or pre-
528
dicted as taken. They fall through if they are not taken or pre-
dicted as not taken.
16
Unit
Opcode
854 SRU
150 SRU
83 SRU
Latency
Cycles Serialization
1 —
2 Completion, refetch
1 —
March 27, 2006
gx_06.fm.(1.2)