Figure 8-12. Normal Single-Beat Write Termination; Figure 8-13. Normal Burst Transaction - IBM PowerPC 750GX User Manual

Figure 8-12. Normal Single-Beat Write Termination

Normal termination of a burst transfer occurs when TA is asserted for four bus clock cycles, as shown in
Figure 8-13. The bus clock cycles in which TA is asserted need not be consecutive, thus allowing pacing of
the data-transfer beats. For read bursts to terminate successfully, TEA and DRTRY must remain negated
during the transfer. For write bursts, TEA must remain negated for a successful transfer. DRTRY is ignored
during data writes.

Figure 8-13. Normal Burst Transaction

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