Data-Transfer Signals; Data Bus (Dh[0-31], Dl[0-31]); Table 7-4. Data-Bus Lane Assignments - IBM PowerPC 750GX User Manual

User's Manual
IBM PowerPC 750GX and 750GL RISC Microprocessor
Timing Assertion
Negation
Data Bus Busy (DBB)—Input
State Asserted
Negated
Timing Assertion
Negation

7.2.7 Data-Transfer Signals

Like the address transfer signals, the data-transfer signals are used to transmit data and to generate and
monitor parity for the data transfer. For a detailed description of how the data-transfer signals interact, see
Section 8.4.3, Data Transfer, on page 303. Data parity is optional on the 750GX.
7.2.7.1 Data Bus (DH[0–31], DL[0–31])
The data bus (DH[0–31] and DL[0–31]) consists of 64 signals that are both inputs and outputs on the 750GX.
State The data bus has two halves—data bus high (DH) and data bus low (DL). See Table 7-4 on
page 266 for the data-bus lane assignments.
Timing The data bus is driven once for noncached transactions and four times for cache transac-
tions (bursts).

Table 7-4. Data-Bus Lane Assignments

Data-Bus Signals
DH[0–7]
DH[8–15]
DH[16–23]
DH[24–31]
DL[0–7]
DL[8–15]
DL[16–23]
DL[24–31]
Signal Descriptions
Page 266 of 377
Occurs the cycle following a qualified DBG. Remains asserted for the dura-
tion of the data tenure.
Negates for a fraction of a bus cycle (one-half minimum, depends on clock
mode) starting the cycle following the final assertion of the transfer
acknowledge (TA) signal, or following the transfer error acknowledge (TEA)
signal or certain ARTRY cases. Then releases to the high impedance state.
Indicates that another master is the current data-bus owner.
Indicates that the data bus might be available for use by the 750GX (see
DBG).
May occur when the 750GX must be prevented from using the data bus.
May occur whenever the 750GX can use the data bus.
Byte Lane
0
1
2
3
4
5
6
7
gx_07.fm.(1.2)
March 27, 2006